Team Alex Bradbury At Igalia since March 2022. Cambridge (UK) Follow me muxup.com fosstodon.org/@asb twitter.com/asbradbury github.com/asb linkedin.com/in/alex-bradbury POSTS May 12, 2024 Notes from the Carbon panel session at EuroLLVM 2024 Last month I had the pleasure of attending EuroLLVM which featured a panel session on the Carbon programming language. It was recorded and of course we all know automated transcription... Continue reading > Feb 20, 2024 Clarifying instruction semantics with P-Code I’ve recently had a need to step through quite a bit of disassembly for different architectures, and although some architectures have well-written ISA manuals it can be a bit jarring... Continue reading > Jan 1, 2024 Reflections on ten years of LLVM Weekly Today, with Issue #522 I’m marking ten years of authoring LLVM Weekly, a newsletter summarising developments on projects under the LLVM umbrella (LLVM, Clang, MLIR, Flang, libcxx, compiler-rt, lld, LLDB,... Continue reading > Dec 24, 2023 Let the (terminal) bells ring out I just wanted to take a few minutes to argue that the venerable terminal bell is a helpful and perhaps overlooked tool for anyone who does a lot of their... Continue reading > Tweets May 2, 2024 RISC-V vector unit configurations: gotta catch ‘em allhttps://github.com/chipsalliance/t1#build May 1, 2024 Slides and video from the ‘CHERITech’ workshop are now available. Well worth a look through. https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/workshops/2024cheritech/Can anyone help decode this... Apr 29, 2024 So how many components are in a normalised target triple?You said four right? Well of course! And apparently Clang has... Apr 24, 2024 I’m surprised this initial support for SWAR vectorisation in LLVM didn’t need more code https://github.com/llvm/llvm-project/pull/69306/filesOf course I also know all... Commits May 15, 2024 [LLVM] [RISCV] Gate unratified profiles behind -menable-experimental-extensi… May 15, 2024 [LLVM] [RISCV][test] Add tests for parsing profiles using RISCVISAInfo::pars… May 14, 2024 [LLVM] [RISCV] Improve constant materialisation for stores of i8 negative co… May 14, 2024 [LLVM] [RISCV][test] Precommit tests for byte store of -1
May 12, 2024 Notes from the Carbon panel session at EuroLLVM 2024 Last month I had the pleasure of attending EuroLLVM which featured a panel session on the Carbon programming language. It was recorded and of course we all know automated transcription... Continue reading >
Feb 20, 2024 Clarifying instruction semantics with P-Code I’ve recently had a need to step through quite a bit of disassembly for different architectures, and although some architectures have well-written ISA manuals it can be a bit jarring... Continue reading >
Jan 1, 2024 Reflections on ten years of LLVM Weekly Today, with Issue #522 I’m marking ten years of authoring LLVM Weekly, a newsletter summarising developments on projects under the LLVM umbrella (LLVM, Clang, MLIR, Flang, libcxx, compiler-rt, lld, LLDB,... Continue reading >
Dec 24, 2023 Let the (terminal) bells ring out I just wanted to take a few minutes to argue that the venerable terminal bell is a helpful and perhaps overlooked tool for anyone who does a lot of their... Continue reading >
May 2, 2024 RISC-V vector unit configurations: gotta catch ‘em allhttps://github.com/chipsalliance/t1#build
May 1, 2024 Slides and video from the ‘CHERITech’ workshop are now available. Well worth a look through. https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/workshops/2024cheritech/Can anyone help decode this...
Apr 29, 2024 So how many components are in a normalised target triple?You said four right? Well of course! And apparently Clang has...
Apr 24, 2024 I’m surprised this initial support for SWAR vectorisation in LLVM didn’t need more code https://github.com/llvm/llvm-project/pull/69306/filesOf course I also know all...